VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
2. All voltages are referenced to V
.
SS
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of t and t . Input signals are changed one time during t . Assume that there are only one read/write
CK
RC
CK
cycle during t (min).
RC
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle t
(min).
CCD
6. Power-up sequence is described in Note 11.
7. A.C. Test Conditions
Reference Level of Output Signals
Output Load
1.4V / 1.4V
Reference to the Under Output Load (B)
Input Signal Levels
3.0V / 0.0V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
3.3V
1.4V
1.2KW
50
W
ZO=50
W
Output
Output
30pF
30pF
870W
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
Document:1G5-0145
Rev.1
Page24
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
