VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
SSTL_3 Interface
Reference Level of Output Signals (VREF)
Output Load
0.45*VDDQ
Reference to the Under Output Load
Input Signal Levels
V
+ 0.4/V
-0.4
REF
REF
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals(V
1ns
0.45*V
)
REF
DDQ
AC Test Load Circuits (for SSTL - 3 interface) :
V
V
= 0.45 * V
DDQ
V
DDQ
TT
DDQ
V
0.45 * V
REF
DDQ
RT2 = 50 Ohms
V
IN
RS = 25 Ohms
V
OUT
Z = 50 Ohms
RT1 = 50 Ohms
C
= 30 pF
LOAD
Device
Under
Test
V
= 0.45 * V
DD
REF
V
= 0.45 * V
DDQ
TT
V
SS
SSTL-3 A.C. Test Load
8. Transition times are measured between V and V . Transition (rise and fall) of input signals are fixed slope (1 ns).
IH
IL
9. t
defines the time at which the outputs achieve the open circuit condition and are not reference levels.
OHZ
10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number)
Document:1G5-0145
Rev.1
Page25
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
