VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Latency relationship to frequency (Unit : clock cycles)
-5 Version (Calculation with t = 5ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RC
RP
RRD
10
1
RAS
30
1
RSC
10
1
RCD
15
1
)
CK
45
2
15
1
30ns
20ns
15ns
10ns
5ns
3
1
1
2
1
1
3
1
1
2
1
1
5
2
1
3
1
2
9
3
2
6
2
3
-6 Version (Calculation with t = 6ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RC
RP
RRD
12
1
RAS
36
2
RSC
12
1
RCD
18
1
)
CK
54
2
18
1
30ns
20ns
15ns
10ns
6ns
3
1
1
2
1
1
4
2
1
3
1
2
6
2
2
4
2
2
9
3
2
6
2
3
-7 Version (Calculation with t = 7ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RC
RP
RRD
12
1
RAS
36
2
RSC
14
1
RCD
20
1
)
CK
62
3
20
1
30ns
20ns
15ns
10ns
7ns
4
1
1
2
1
1
5
2
1
3
1
2
7
2
2
4
2
2
9
3
2
6
2
3
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V and V (simultaneously) when all input signals are held “NOP”
DD
DDQ
state and CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that
DQM is held “high” (V levels) to ensure DQ output to be in the high impedance.
DD
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device. Sequence of 4 and 5 may be changed.
Document:1G5-0145
Rev.1
Page26
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
