VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Recommended D.C. Operating Conditions (V = 3.3V ±0.3V, Ta = 0 ~ 70¢J)
DD
-5
-6
-7
Unit Note
Description/test condition
Symbol
Min. Max. Min. Max. Min. Max.
Operating Current
³ t , Outputs Open
1 bank
operation
I
190
170
150
3,4
DD1
t
RC
RC(min)
Address changed once during t
.
CK(min)
Burst Length = 1
Precharge Standby Current in non-power down mode
= t , CS ³ V , CKE ³ V
I
35
15
35
15
35
15
3
DD2N
t
CK
CK(min)
(min)
(min)
IH
IH
Input signals are changed once during 30ns.
Precharge Standby Current in non-power down mode
I
DD2NS
t
= ¥ , CKE ³ VIH
, CLK £ V
IL
CK
(min)
(max)
mA
Input signals are stable
Precharge Standby Current in power down mode
= t (min), CKE £ V
I
2.0
2.0
2.0
2.0
2.0
2.0
3
DD2P
t
CK
CK
(max)
IL
Precharge Standby Current in power down mode
= ¥ , CKE £ V
, CLK £ V
I
DD2PS
t
CK
(max)
(max)
IL
IL
Active Standby Current in non power down mode
CKE ³ VIH , t = t
I
4
4
4
3
DD3P
(min) CK
CK(min)
Active Standby Current in power down mode
CKE £ VIL , t , CS ³ V
I
30
30
30
DD3N
t
(max) CK = CK(min)
IH(min)
Operating Current (Page Burst, and All Bank activated)
= t , Outputs Open, Multi-bank interleave, gapless
I
I
220
200
170
4,5
3
DD4
t
CCD
CCD(min)
data
Refresh Current
190
170
140
DD5
tRC ³ tRC
(min)
Self Refresh Current
CKE £ 0.2V
I
I
1
1
1
DD6
Operating Current (Block Write)
250
230
190
DD7
t
= t
, Outputs Open, t
= t
CK
CK(min)
BWC BWC(min)
Parameter
Description
Input Leakage Current
Min.
Max.
Unit
Note
I
-5
5
mA
IL
(0V £ V £ V
All other pins not under test = OV)
IN
DD
I
Output Leakage Current
-5
5
mA
OL
Output disable, (0V £ V
£ V
)
OUT
LVTTL Output ”H” Level Voltage
(l = -2mA)
DDQ
V
2.4
-
-
0.4
-
V
V
V
V
OH
OUT
V
LVTTL Output ”L” Level Voltage
(l = 2mA)
OL
OUT
V
SSTL Output ”H” Level Voltage
(l = -16mA)
V
+0.8
TT
OH
OUT
V
SSTL Output ”L” Level Voltage
(l = 16mA)
-
V
+0.8
TT
OL
OUT
Document:1G5-0145
Rev.1
Page22
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
