VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
A11(BS)
RAa
RAa
RBa
RBa
A10
A0~A9
CBa
CBb
CBc
CAa
CAb
CBd
t
t
t
RCD
DPL
DPL
DQM
DQ
t
t
RRD
RP
Hi-Z
DBa0 DBa1 DBb0
DBc0 DBc1 DAb0
DAb1 DAd0 QAd1 QAd2 QAd3
DAa3
DBb1
DAa0 DAa1
DAa2
Write
Write
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Write
Write
Precharge
Command
Bank B
Write
Command
Bank B
Command Command
Bank B
Command Command
Bank B
Bank B
Activate
Command
Bank B
Precharge
Command
Bank A
Document:1G5-0189
Rev.1
Page54