VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
A11(BS)
RAa
RAa
RBa
RBa
A10
A0~A9
CBa
CBb
CBc
CAa
CAb
DQM
DQ
t
RCD
t
AC3
t
RRD
Hi-Z
QBa0 QBa1 QBb0
Read
QBc0 QBc1 QAb0
Precharge
QAa3
QBb1
Read
QAb1 QAb2
QAb3
QAa0 QAa1
QAa2
Activate
Command
Bank A
Read
Command
Bank A
Read
Read
Precharge
Command
Bank A
Command Command
Command Command
Command
Bank B
Bank B
Bank A
Bank B
Bank B
Activate
Command
Bank B
Document:1G5-0189
Rev.1
Page52
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
