VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Read Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
A11(BS)
RAa
RAa
RBa
RBa
A10
A0~A9
CBa
CBb
CBc
CAb
CBd
CAa
t
t
DQM
DQ
AC2
RCD
Hi-Z
QBa0 QBa1 QBb0
QBc0 QBc1 QAb0
QAb1 QBd0 QBd1
QAa3
QBb1
QAa0 QAa1
QBd2 QBd3
QAa2
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Read
Command
Bank B
Precharge
Command
Bank B
Command
Bank B
Precharge
Command
Bank A
Document:1G5-0189
Rev.1
Page51