VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and deserialize the
data stream to a 32 bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered clock to
serialize its transmit data words that are sent to the switch. In this way, the switch and all the transceivers are
frequency-locked to one clock source which is provided by the word clock on the switch card. The transceiver
provides its own CMU which multiplies a local REFCLK by 34. The output of the CMU helps the CRU obtain lock
and provides the clock source for the transceiver in loopback mode. This local REFCLK must be within 100ppm of
the switch chip reference clock frequency. In Direct Mode, the master transceiver uses the CMU to provide a clock
for the transmit data. The slave receivers recover the clock from the serial bit streams.
1.1.4 Word Synchronization
During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver
sends reset patterns to the switch (or the master transceiver in Direct mode) to request that the switch starts the
initialization process. The switch, upon receiving this request, will send out special ALIGN words. The transceiver
receives this serial data stream from the switch, and uses the RXCLK Generator to adjust the receive word clock
boundary one bit at a time until the Word/Cell Aligner detects proper alignment. Upon detecting the correct word
alignment, the RXOK signal is set LOW and the word alignment process is started on the transmit side. In this
process, the transceiver continuously sends ALIGN words to the switch using the Alignment Word Generator. The
switch uses its own word clock to detect this ALIGN word. If the transmitters word is not aligned to the switch chip
word clock when it arrives at the switch, the switch chip continues to send out ALIGN words. After receiving every
32 ALIGN words from the switch chip, the transceiver changes its transmit word boundary by one bit position using
the TXCLK Generator and then repeats the process (this limits the distance from the transceiver to the switch to less
then 180nS one way). If the switch detects this ALIGN word correctly, it sends IDLE words to the transceiver to
signal that the transmitter has now word synchronized with the switch. When the transceiver detects these IDLE
words, the signal TXOK goes LOW and the parallel data signals TXIN[31:0], TXTYP[1:0], RXOUT[31:0] and
RXTYP[1:0] are then phase aligned to the word clock (WSOUT).
The transmit word clock is output on the pin WSOUT. If a single transceiver is used on a port card, WSOUT
must be tied directly to WSIN. The signal WSIN is the clock input for all of the transceiver parallel logic and
provides the word clock output (WCLK). Retiming blocks are used in the transceiver to span the phase boundary
between WSIN and the transmit word clock and the receive word clock. If two or more transceivers are used in
parallel on a port card in order to increase bandwidth, each will have its own transmit word clock. Since these word
clocks are derived from the same source on the switch card, they will have the same frequency but a phase difference
of up to 8nS. This phase difference (skew) depends on the I/O delay of the switch and transceiver and the serial data
line delay between these chips. To properly phase align all transceiver parallel interfaces, one transceiver acts as the
master, providing its WSOUT signal not only to its own WSIN, but the WSIN on all other transceivers on the port
card (see Application Note 32: Design Guide for a Cell Based Switch with Central Control). This means that the
parallel logic blocks on all transceivers are clocked by the same source derived from the transmit word clock of the
master transceiver. In this way, skew between the parallel interfaces on all transceivers is minimized. Other logic on
the port card can be clocked using WSOUT of the master transceiver, or the WCLK output of any transceiver which
is a delayed version of WSOUT. A phase shifted word clock can also be used to drive WSIN provided that it is
frequency locked to the WSOUT signal. In this way, both the receive and transmit parallel interfaces can be phase
aligned to this word clock.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52190-0, Rev 4.1
01/05/01
Page 7
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Internet: www.vitesse.com
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