VITESSE
SEMICONDUCTOR CORPORATION
High Performance Serial
Backplane Transceiver
Freq
Type
Data Sheet
VSC870
I/O
Description
When RXSEL is LOW and LOOPBACK is LOW, RXSA
is selected as the input to the CRU and RXSB is selected
as the input to the Signal Detector. When RXSEL is
HIGH and LOOPBACK is LOW, RXSB is selected as the
input to the CRU and RXSA is selected as the input to the
Signal Detector.
This output is high if at least one edge transition is
detected every word clock period on the redundant input
serial line.
This signal goes LOW if the VSC870 is word aligned on
the receive side. After initialization, it goes HIGH if there
is error in the IDLE words.
When RXEN is LOW, the RXOUT[31:0] and
RXTYP[1:0] outputs become high impedance.
32-bit parallel data output for the receive side.
If BYPASS is LOW, these signals tell the received word
type. If BYPASS is HIGH, these signals reflect the
overhead bits received on the serial channel.
When RXWA is LOW, RXTYP[1:0] and RXOUT[31:0]
is an IDLE word.
In Packet Mode, the ACK signal will be set high if a
Connection Request on the transmit side is granted. In
Cell mode, a high pulse represents the receive cell clock.
When BYPASS is LOW and ABORT is HIGH, the
connection request and data transmission process is
aborted.
The WSIN signal provides the word clock input and must
be driven by a signal frequency locked to the WSOUT
signal either from itself or another transceiver.
The WSOUT signal is the internally generated word clock
and is synchronized to the transmit word clock.
If RESYNEN is HIGH and the transceiver detects a link
error, it will start the Link Initialization process.
If OOS is HIGH, the transceiver is in the link
initialization process. It is LOW during normal operation.
If SCRAM is HIGH, data words will be scrambled and
descrambled.
BYPASS is set HIGH for direct control and monitoring of
the overhead bits in the serial data streams as in cell mode
and direct mode. This also disables the transceiver Packet
Mode functions.
CELLSYN is set HIGH to allow cell synchronization
during link initialization.
Symbol
Name
RXSEL
Receive Input Select
I
<1MHz
TTL
ALIVE
Redundant Input Alive
O
<1MHz
TTL
<1MHz
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5MHz
TTL
62.5MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
RXOK
RXEN
RXOUT[31:0]
RXTYP[1:0]
RXWA
ACK/RCLK
Receive Signal OK
Receive Enable
Receive Parallel Data
Out
Receive Word Type
Receive Word Available
Acknowledge /
Receive Cell Clock
Connection Request
Abort
Word Synch In
Word Synch Out
Resync Enable
Out Of Sync
Scramble Enable
O
I
O
O
O
O
ABORT
I
WSIN
WSOUT
RESYNEN
OOS
SCRAM
I
O
I
O
I
BYPASS
Bypass Mode
Cell Synchronization
Enable
I
CELLSYN
I
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52190-0, Rev 4.1
01/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
