VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC870
Symbol
DLYEN/
CCKIN
FACLPBK
WCLK
High Performance Serial
Backplane Transceiver
Freq
Type
<1MHz
TTL
<1MHz
TTL
62.5MHz
TTL
62.5MHz
TTL
<1MHz
TTL
<1MHz
TTL
62.5Mb/s
TTL
<1MHz
TTL
3.3V
0V
Name
Delay Enable/Cell Clock
Input
Facility Loopback
Word Clock
I/O
Description
If BYPASS is LOW, this signal can be set HIGH to enable
REN delay mode. In Cell Mode, DLYEN/CCKIN can be
used as an input for cell clock alignment.
When this signal is HIGH, the serial input is looped back
to the serial output. It should be normally set LOW.
The word clock is a delayed version of the WSIN signal.
A 62.5 MHz local reference clock that is used to keep the
CRU close to the incoming bit clock frequency before the
alignment process begins. Is also used as a reference
clock for the CMU.
Global chip reset (active HIGH).
When TESTEN is HIGH, the REFCLK is used in place
of the bit clock for low speed testing. Used for ATE
testing only. Set to logic LOW during normal operation.
LTIME is set HIGH to use the recovered bit clock for the
transmit side.
Used for ATE testing of the parametric NOR chain in the
I/O frame. Set to logic LOW during normal operation.
Clean power supply for CMU
Clean ground for CMU
I
I
O
REFCLK
Local Reference Clock
I
RESET
TESTEN
LTIME
VSCTE
VDDA
VSSA
Reset
Scan Test Enable
Loop Time Mode
NOR Chain Test Enable
CMU Power Supply
CMU Ground
I
I
I
I
P
P
G52190-0, Rev 4.1
01/05/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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