VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
1.3 Loopback Mode
The VSC870 supports two loopback functions at the serial interface. If the LOOPBACK signal is set HIGH, the
serial transmit data is looped back to the CRU on the serial receiving side. The transmitted serial data is generated
using the CMU clock. This mode can be used to test the high speed circuitry (except for the serial input/output
buffers) using the low speed parallel interface. The serial data can also be looped back through the I/O of the switch
chip or other connected transceiver if the other device is in FACLPBK mode (see the table below). If FACLPBK is set
HIGH, the receive serial data is recovered using the CRU and looped back to the serial output.
1.4 Redundancy
There are two serial output buffers and two serial input buffers on the transceiver. These can be used to connect
to redundant switch chips or redundant transceivers. The serial inputs are also connected to a signal detector circuit
which is used to determine if there is an average of one transition for every 34 bits of data. If there is, the signal
ALIVE remains HIGH. Which ever input is not connected to the CRU is connected to the signal detector. An example
system would have the redundant serial output connected to a redundant switch chip. This switch chip has the LPBK
bits in the status and control registers set HIGH such that the transceiver output signal (which is looped through the
switch input/output buffer) comes back to itself at the redundant serial input buffer (see Application Note 35). If the
primary switch chip fails, and the ALIVE signal is HIGH on all transceivers, the redundant switch chip can be
activated in its place after it goes through the link initialization process. The signal RXSEL on the transceiver is used
to select the redundant input buffer.
1.5 Operating Modes
The following table summarizes the operating modes for the transceiver that have been discussed in the previous
sections. The pin LTIME selects the source of the bit clock for the transmit side. LTIME is normally set HIGH. In this
case, the received bit clock is use for the transmit bit clock. If LTIME is set LOW, the transceivers CMU is used as the
source of the transmit bit clock. This signal must be set LOW to test the transceiver in loopback mode or when used
as a master transceiver in Direct Mode (see section 4.0).
Control Signal Name
Description of Operation
LOOP
BACK
BY
PASS
CELL
SYN
LTIME
MODE[1]
MODE[0]
0
0
0
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
X
1
1
0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
Normal Packet Mode operation
Normal Cell Mode operation
Master transceiver in Direct Mode (figure 13)
Slave transceiver in Direct Mode (figure 13)
Master transceiver in Direct Mode (figure 14)
Slave transceiver in Direct Mode (figure 14)
Loopback mode internal to the transceiver
Loopback mode through a VSC880
Loopback mode through an external cable
Mux/Demux Mode - No word alignment
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52190-0, Rev 4.1
01/05/01
Page 11
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