VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
ALMOST_FULL signal from the receiving FIFO is connected to the RTR pin, and the REN signal is connected to the
transmitting FIFO READ_ENABLE signal. In this way, when the receive FIFO is almost full, the transmit FIFO will
be disabled from sending data. For multicast, all incoming flow control data is ORed to the transmitting port.
The latency from the time the backpressure is applied at the RTR pin until the REN output at the transmitting
port card is asserted is 9 clock cycles. This number can be 5 cycles longer if the flow control channel is temporarily
interrupted by the ACK or Multi Queue response bits. When using early arbitration, during the time between the early
CRQ and the header, the transceiver ignores the flow control bits. This time is D word clock cycles. The maximum
latency is therefore D+14 cycles not including the serial transmission line delays. This means that the receive FIFO
must signal an almost full condition at least D+14 words before the full condition is reached. This can be larger if the
transceivers are more than 16 nS away from the switch chip.
Back pressure is not supported in transceiver loopback mode.
2.6 Packet Mode with BYPASS set HIGH
When the signal BYPASS is HIGH, most of the logic functions described in this section are disabled. In this
mode, the transceiver acts as a 34:1 MUX using TXTYP[1:0] as the two MSBs, and a 1:34 DEMUX using
RXTYP[1:0] as the two MSBs. The data presented at the parallel interface will get serialized on the transmit side
without any modification to the overhead bits, and the reverse is true for the receive side. In this mode, it is up to the
user to make sure the data transmitting from the transceiver conforms to the format of the 34-bit command words that
are recognizable by the VSC880. The format of the 34-bit command words to and from the switch chip can be found
in the VSC880 data sheet. This mode allows the user to define logic to implement specialized packet mode functions
that are not implemented in the transceiver logic. See section 4.0 for more information.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52190-0, Rev 4.1
01/05/01
Page 25
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Internet: www.vitesse.com
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