VSC8601 Datasheet
Configuration
4.3.6
Extended PHY Control 3
Register 20E controls the ActiPHY sleep timer, its wake-up timer, the frequency of the
CLKOUT signal, and its link speed downshifting feature. The following table lists the
settings available.
Table 41.
Extended PHY Control 3, Address 20E (0x14)
Bit
Name
Access Description
Default
15
Reserved
RO
14:13 ActiPHY sleep timer
R/W
This is a sticky bit.
01
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.
12:11 Reserved
RO
10:9
ActiPHY link status
time-out control
R/W
00 = 1 second.
01 = 2 second.
10 = 3 second.
11 = 4 second.
01
8:6
5
Reserved
RO
MAC RX_CLK
Disable
R/W
1 = RX_CLK is held low.
0 = RX_CLK is in normal operation.
0
4
Enable link speed
auto-downshift
feature
R/W
R/W
This is a sticky bit.
1 = Enable auto link speed downshift from
1000BASE-T.
CMODE
3:2
Link speed
auto-downshift
control
This is a sticky bit.
00 = Downshift after two failed 1000BASE-T
auto-negotiation attempts.
01
01 = Downshift after three failed 1000BASE-T
auto-negotiation attempts.
10 = Downshift after four failed 1000BASE-T
auto-negotiation attempts.
11 = Downshift after five failed 1000BASE-T
auto-negotiation attempts.
1
0
Link speed
auto-downshift
status
RO
RO
0 = No downshift.
1 = Downshift is required or has occurred.
0
Reserved
4.3.7
EEPROM Interface Status and Control
Register 21E is used to affect control over device function when you have incorporated
a startup EEPROM into your design.
Table 42.
EEPROM Interface Status and Control, Address 21E (0x15)
Bit
Name
Access Description
Default
15
Reserved
RO
Revision 4.1
September 2009
Page 59
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
