VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
Figure 16: High-Speed Clock and High-Speed Data Inputs
Chip Boundary
VCC = 3.3V
1.65V
3kΩ
3kΩ
3kΩ
3kΩ
1.65V
ZO
CIN
CAC
CIN
50Ω
50Ω
VTERM
ZO
VEE = 0V
CIN TYP = 100nF
AC TYP = 100nF
C
High-Speed Clock and High-Speed Data Inputs
The incoming high-speed data and high-speed clock are received by high-speed inputs RXIN and
RXCLKIN. The inputs are internally biased to accommodate AC-coupling.
The data input receiver is internally terminated by a center-tapped resistor network. For differential input
DC-coupling, the network is terminated to the appropriate termination voltage VTERM providing a 50Ω to VTERM
termination for both true and complement inputs. For differential input AC-coupling, the network is terminated
to VTERM via a blocking capacitor.
In most situations, these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology, as shown in Figure 16. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-
coupling operations, it is recommended that the user provides an external reference voltage which has better
temperature and power supply noise rejection than the on-chip resistor divider. The external reference should
have a nominal value equivalent to the common-mode switch point of the DC-coupled signal, and can be con-
nected to either side of the differential gate.
Page 12
VITESSE SEMICONDUCTOR CORPORATION
G52251-0, Rev. 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
9/6/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
