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VSC8140TW 参数 Datasheet PDF下载

VSC8140TW图片预览
型号: VSC8140TW
PDF下载: 下载PDF文件 查看货源
内容描述: 2.48832Gb / s的16 : 1 SONET / SDH收发器,集成时钟发生器 [2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator]
分类和应用: 时钟发生器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 34 页 / 530 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE  
SEMICONDUCTOR CORPORATION  
Data Sheet  
2.48832Gb/s 16:1 SONET/SDH  
Transceiver with Integrated Clock Generator  
VSC8140  
When LOOPTIM1 is asserted high, the RXCLK16_32O or RXCLK16O output can be tied to the LPTIM-  
CLK input. In order to meet jitter transfer, the RXCLK16_32O or RXCLOCK16O needs to be filtered by a 1X  
PLL circuit with a narrow pass characteristic. The part is forced out of this mode in Equipment Loopback to  
prevent the PLL from feeding its own clock back.  
Clock Generator  
An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input.  
The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip  
loop filter (with two external 0.1µF peaking capacitors). The loop bandwidth of the PLL is within the SONET  
specified limit of 2MHz.  
The customer can select to provide either a 77.76MHz reference, or 2x of that reference, 155.52MHz.  
REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0” designates REFCLK  
input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz.  
The REFCLK should be of high quality since noise on the REFCLK below the loop bandwidth of the PLL  
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a  
VCXO may be required to avoid passing REFCLK noise with greater than 2ps RMS of jitter to the output. The  
VSC8140 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8140 itself during such  
conditions.  
Loop Filter  
The PLL on the VSC8140 employs an internal loop filter with off-chip peaking capacitors. The PLL design  
is fully differential, therefore the loop filter must also be fully differential. One capacitor should be connected  
between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended  
capacitors are low-inductance 0.1µF 0603 ceramic SMT X7R devices with a voltage rating equal to or greater  
than 10V.  
Figure 13: High-Speed Output Termination  
VCC  
50  
50Ω  
100Ω  
Z0 = 50Ω  
Pre-Driver  
VEE  
G52251-0, Rev. 4.0  
9/6/00  
VITESSE SEMICONDUCTOR CORPORATION  
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896  
Page 9  
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