VITESSE
SEMICONDUCTOR CORPORATION
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Figure 11: Equipment Loopback Data Path
RXIN+
RXIN-
RXCLKIN+
RXCLKIN-
EQULOOP
TXOUT+
TXOUT-
TXCLKOUT+
TXCLKOUT-
2.48832GHz
PLL
D Q
0
1
0
1
1:16 Serial to
Parallel
Data Sheet
VSC8140
RXOUT[15:0]
RXCLK16O
RXCLK32O
TXIN[15:0]
Q D
16:1 Parallel to
Serial
TXCLK16I
TXCLK16O
Figure 12: Split Loopback Datapaths
RXIN+
RXIN-
RXCLKIN+
RXCLKIN-
D Q
0
1
0
1
1:16 Serial to
Parallel
RXOUT[15:0]
RXCLK16O
RXCLK32O
TXOUT+
TXOUT-
TXCLKOUT+
TXCLKOUT-
FACLOOP
Q D
1
0
1
0
16:1 Parallel to
Serial
TXIN[15:0]
TXCLK16I
TXCLK16O
2.48832GHz
PLL
EQULOOP
Split Loopback
Equipment and Facility Loopback modes can be enabled simultaneously. In this case, high-speed serial data
received (RXIN) and clock (RXCLKIN) are muxed through to the high-speed serial outputs (TXOUT and
TXCLKOUT). The low-speed 16-bit transmit stream (TXIN[15:0]) is muxed into the low-speed 16-bit receive
output stream (RXOUT[15:0]). See Figure 12.
Looptiming
LOOPTIM0 mode bypasses the PLL when LOOPTIM0 is asserted high. In this mode, the PLL is bypassed
using the receive high-speed clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
Page 8
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52251-0, Rev. 4.0
9/6/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
