VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
Figure 22: Receiver AC Timing Waveforms
RXCLK16O+
Parallel Data Clock Output
tRXPDD
tRXDSU
Valid Data 1
RXOUT[0:15]+
Parallel Data Outputs
Valid Data 2
tRXPD32
RXCLK32O+
Parallel Data Clock Output
= don’t care
Figure 23: Receiver Setup and Hold Time Requirements
tRXDSU
tRXDH
RXIN+
D13
D1
D0
D15
D14
Differential Serial Data Input
LSB
MSB
Time
RXCLKIN+
Differential Clock Input
NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.
Table 2: Receiver AC Characteristics
Parameters
Description
Min Typ Max
Units
Conditions
Data valid from falling edge of
RXCLK16O+
tRXPDD
0
0
800
1.0
300
250
55
ps
—
—
RXCLK32O transition from
falling edge of RXCLK16O+
tRXPD32
ns
ps
ps
RXOUT[15:0]+/- rise and fall
times
20% to 80% into DC termination.
See Figure 24.
t
RXDR, tRXDF
—
—
45
100
tRXCLKR
tRXCLKF
,
RXCLK16O+/- rise and fall
times
20% to 80% into 100Ω load.
See Figure 24.
RXCLK16O+/- duty cycle
distortion
% of
clock cycle
High-speed clock input at
2.48832GHz.
RXCLK16OD
tRXDSU
RXIN+ setup time with respect
to falling edge of RXCLKIN+
—
ps
ps
—
—
—
RXIN+ hold time with
respect to falling edge of
RXCLKIN+
tRXDH
75
40
—
60
RXCLKIN+/- duty cycle
distortion
% of
clock cycle
RXCLKIND
Page 16
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52251-0, Rev. 4.0
9/6/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
