VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
AC Characteristics
Figure 18: Transmitter Parallel Data Timing Waveforms
TXCLK16I+
Parallel Data Clock Input
tTXDSU
tTXDH
TXIN[0:15]+, TXPRTYIN
Parallel Data Inputs
Valid Data 1
Valid Data 2
TXCLK16O+
Parallel Data Clock Output
= don’t care
Figure 19: Transmitter Serial Data and Clock Phase Timing
tDH
TXOUT+
Differential Serial Data Output
D13
D1
D0
D15
D14
LSB
MSB
Time
tPD
TXCLKO+
Differential Clock Output
NOTE: Bit 15 (MSB) is transmitted first, Bit 0 (LSB) is transmitted last.
Figure 20: Transmitter Parity Timing
tD
TXCLK16I+
Parallel Data Clock Input
tDV
tD
PARERR+
Data Valid Output
Page 14
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52251-0, Rev. 4.0
9/6/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
