VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
Transmitter High-Speed Data and Clock Outputs
The high-speed data and clock output drivers (TXOUT and TXCLKOUT) consist of a differential pair
designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100Ω resistor at
the load between true and complement outputs (see Figure 13). No connection to a termination voltage is
required. The output driver is back terminated to 50Ω on-chip, providing a snubbing of any reflections. If used
single-ended, the high-speed output driver must still be terminated differentially at the load with a 100Ω resistor
between true and complement outputs.
In order to save power, the high-speed transmit clock output (TXCLKOUT) can be powered down by con-
necting the power pins VEEP_CLK and VEE_PWRDN to the V supply instead of to V
.
EE
CC
Figure 14: AC Termination of Low-Speed LVPECL REFCLK and LPTIMCLK Inputs
Chip Boundary
VCC = 3.3V
R1||R2 = Zo , R1 = 83Ω R2 =125Ω
V
CC
V
R2 + V R1
CC
EE
= V
R1
R2
BIAS
R1+R2
ZO
CIN
V
EE
V
V
CC
R1
R2
ZO
CIN
EE
VEE = 0V
CIN TYP = 100nF
for AC operation
Reference Clock Inputs
The incoming low-speed reference clock inputs are received by differential LVPECL inputs REFCLK± .
Off-chip termination of these inputs is required (see Figure 14).
In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial clock inputs have the same circuit topol-
ogy, as shown in Figure 14. If the input signal is driven differentially and DC-coupled to the part, the mid-point
of the input signal swing should be centered about the input common-mode voltage V
and not exceed the
CM
maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user pro-
vides an external reference voltage. The external reference should have a nominal value equivalent to the com-
mon-mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.
Page 10
VITESSE SEMICONDUCTOR CORPORATION
G52251-0, Rev. 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
9/6/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
