VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
Figure 21: Differential and Single-Ended Input / Output Voltage Measurement
b
a
Single
Ended
Swing
=
α
b
=
Differential α
Swing
a
* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single-ended swing.
Differential swing is specified as equal in magnitude to single-ended swing.
Table 1: Transmitter AC Characteristics
Parameters
TD
Description
Min
Typ
Max Units
Conditions
TXCLK16I/TXCLK16O period
—
6.4
—
—
ns
ns
—
—
Data setup time to the rising edge of
TXCLK16I+
TTXDSU
TTXDH
0.75
1.0
—
—
Data hold time after the rising edge
of TXCLK16I+
—
ns
—
TTXDOR
TTXDOF
,
20% to 80% into 100Ω load.
See Figure 13.
TXOUT± rise and fall time
Transmit clock duty cycle
TXCLK16O± rise and fall times
TXCLK16O± duty cycle
TXCLK16I± duty cycle
—
40
—
46
35
—
—
—
—
—
120
60
ps
%
ps
%
%
TXCLKD
—
tTXCLK16R
tTXCLK16F
,
250
53
See Figure 24
—
TXCLK16OD
TXCLK16ID
Assuming 10% distortion of
TXCLK16O.
65
RCKD
TDV
Reference clock duty cycle
Parallel data to DINVALID
TXCLKO period
40
—
—
—
60
—
—
%
ns
ps
—
—
—
3 tD + 0.3
401.9
tDH
Center of output data eye from
falling edge of TXCLKO
tPD
-75
—
—
+75
ps
See Figure 19
Clock Multiplier Performance
RMS, tested to SONET
specification (12kHz to
20MHz) with 2ps RMS jitter
on REFCLK.
TDJ
Output data jitter
Output clock jitter
—
—
4
4
ps
ps
RMS, tested to SONET
specification (12kHz to
20MHz) with 2ps RMS jitter
on REFCLK.
TCJ
—
—
Jittertol
Jitter tolerance
Tuning Range
—
—
—
Exceeds SONET/SDH mask
-100
+100
ppm
G52251-0, Rev. 4.0
9/6/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 15
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