VSC7216-02
Data Sheet
Table 18. General Receive AC Characteristics (continued)
Symbol Parameter
DJTD Receive data deterministic jitter
Min
Max
Units Condition
FC-PI Rev 6.6. Tested on a
370
ps
tolerance (p-p)
sample basis.
1. The probability of correct data acquisition and recovery is 95% per FC-PH 4.3 Section 5.3.
t
H
VIH(MIN)
VIL(MAX)
REFCLK
tL
Figure 24. REFCLK Timing Waveform
Table 19. Reference Clock Requirements
Symbol
Parameter
Min
98
Typ
Max
136
68
Unit
Condition
MHz Full rate
MHz Half rate
FR
Frequency range
49
FO
Frequency offset
| REFCLK (Tx) – REFCLK
(Rx) | = max offset between
Tx and Rx device.
–200
200
65
ppm
REFCLK’s on one serial link
DC
REFCLK duty cycle
35
3
%
Measured at 1.4V.
tH, tL
REFCLK and TBC pulse width
REFCLK rise and fall time
ns
t
RCR,tRCF
Between VIL(MAX) and
1.5
ns
ps
VIH(MIN)
.
REFCLKJITTER REFCLK jitter power
Peak-to-peak jitter at
VSC7216-02’s REFCLK
input between 100Hz and
3Hz.
100
VDD
VSC7216-02
50Ω
50Ω
REFCLKN
0.1µF
Figure 25. REFCLKN Termination When Single-Ended LVTTL Clock is Used at REFCLKP
27 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
