VSC7216-02
Data Sheet
TBCn
(or TBCA)
Internal Clock
(from PLL)
t
t
S
S
Tn[7:0]
C/Dn
Valid
Valid
Valid
WSENn
Figure 17. Transmit Input Timing Waveforms with TMODE = 11X (ASIC-Friendly Timing)
Table 13. Transmit Input AC Characteristics with TMODE = 11X
Symbol
Parameter
Min
Typ
Max
Units
Condition
tS
Input Skew relative to the rising edge of
TBCn or TBCA
2.0
bc
Measured between the
valid data level of the
input andthe1.4V point
of TBCn or TBCA.
bc = bit clock.
t
t
SDR, SDF
TX0
TXn+, TXn–
t
LAT
REFCLK
(or TBCn)
Figure 18. Transmit Serial Timing Waveforms
Table 14. Transmit Serial AC Characteristics
Symbol
Parameter
Min
Typ
Max
Units Condition
Measured between 20% to
80% of the valid data level.
tSDR, tSDF TXn+/- rise and fall time
330
ps
tLAT
Latency, REFCLK to TX0
Latency, TBCA to TX0
22bc+0.2ns
36bc+0.1ns
32bc+1.0ns
22bc+1.8ns bc + ns ENDEC = 1, TMODE = 000.
38bc+1.8ns bc + ns ENDEC = 1, TMODE = 10X.
42bc+1.8ns bc + ns ENDEC = 1, TMODE = 101.
FC-PI Rev 6.6. Tested on a
Latency, TBCB/C/D to TX0
tJ
Serial data output
Total jitter (p-p)
192
ps
sample basis.
tDJ
Serial data output
FC-PI Rev 6.6. Tested on a
sample basis.
80
ps
Deterministic jitter (p-p)
23 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
