VSC7216-02
Data Sheet
t
4
t
3
RCLKn
RCLKNn
Figure 22. RCLKn and RCLKNn Timing Waveforms with DUAL = 1
REFCLK
RCLK
RX1 RX0
RX
RLAT
Figure 23. R
Timing
LAT
Table 18. General Receive AC Characteristics
Symbol Parameter
Min
Max
Units Condition
TRX is the bit period of the
t3
Delay between rising edge of RCLKn to
rising edge of RCLKNn
10 • TRX – 500 10 • TRX + 500
ps
ps
ps
%
incoming data on Rx.
Δt3
RCLKn to RCLKNn skew
Deviation of RCLKn rising edge
to RCLKNn rising edge. Nominal
delay is 10 bit times.
10
–500
500
Delay= -------------- ΔT
3
f
baud
t4
Period of RCLKn and RCLKNn
Whether or not locked to serial
data, independent of DUAL input.
0.99 • tREFCLK 1.01 • tREFCLK
Δt4
Deviation of RCLK/RCLKN period from
REFCLK period
Whether or not locked to serial
data, independent of DUAL input.
–1.0
1.0
2.4
tRCLK= tREFCLK Δt4
tR, tF
RLAT
RCLK output rise and fall times
Between VIL(MAX) and VIH(MIN)
into 10pF load.
ns
Latency from RX0 to REFCLK or RCLK
Latency from RX0 to REFCLK or RCLK
Latency from RX0 to REFCLK or RCLK
70.5bc -1.6ns 81.5bc + 4.1ns
48.5bc - 1.6ns 102.5bc + 4.1ns bc+ns ENDEC = X, Recenter + drift
RXFIFO[0:1] = 01
ENDEC = 1, Recenter only
76
38
92
151
ENDEC = 1, Recenter only
ENDEC = X, Recenter + drift
RXFIFO[0:1] = 00 at 1.36Gb/s
ns
ns
47
38
63
151
ENDEC = 1, Recenter only
ENDEC = X, Recenter + drift
RXFIFO[0:1] = 11 at 1.36Gb/s
(1)
tLOCK
Data acquisition lock time
Using K28.5+/K28.5- pattern.
Tested on a sample basis.
(dt = data transitions).
128
600
dt
TJTD
Receive data total jitter tolerance (p-p)
FC-PI Rev 6.6. Tested on a
sample basis.
ps
26 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
