VSC7216-02
Data Sheet
Table 23. Pin Identifications
Pin
Name
I/O
Type
Description
6Y, 8U,
7W, 5Y,
7V, 7U,
6W, 5W
TA[7:0]
I
TTL
Transmit Data for Channel n, Synchronous to REFCLK, TBCA or TBCn.
Transmit Data for Channel n, Synchronous to REFCLK, TBCB or TBCn.
Transmit Data for Channel n, Synchronous to REFCLK, TBCC or TBCn.
Transmit Data for Channel n, Synchronous to REFCLK, TBCD or TBCn.
11U, 11W,
10Y, 10W,
10U, 10V,
9Y, 9W
TB[7:0]
TC[7:0]
TD[7:0]
I
I
I
I
TTL
TTL
TTL
TTL
12A, 11C,
11D, 10A,
10B, 10D,
10C, 9A
8D, 8C,
7B, 5A,
7D, 6B,
6C, 5B
7Y
11V
12B
6A
C/DA
C/DB
C/DC
C/DD
Control/Data for Channel n. If KCHAR = C/Dn = LOW, then Tn[7:0] is used to
generate transmit data. If KCHAR = C/Dn = HIGH then special Kxx.x
characters are transmitted based upon the value of Tn[7:0]. If KCHAR = LOW
and C/Dn = HIGH, IDLE characters are transmitted.
When ENDEC = LOW, this is equivalent to data bit Tn8.
8Y
12Y
12C
8B
WSENA
WSENB
WSENC
WSEND
I
TTL
Word Sync Enable for Channel n. Asserted HIGH for one cycle to initiate
transmission of the Word Sync Sequence as defined in Figure 5 on page 7
and related text.
When ENDEC = LOW, this is equivalent to data bit Tn9.
9U
9V
9B
9C
TBCA
TBCB
TBCC
TBCD
I
I
TTL
TTL
Transmit Byte Clock for Channel n. Optional input data timing reference for
Tn[7:0], WSENn and C/Dn.
12W
KCHAR
Special Kxx.x Character Enable. When C/Dn is HIGH, KCHAR controls data
sent to the transmitter. When LOW, IDLE characters are sent. When HIGH,
Kxx.x special characters are sent as encoded on Tn[7:0]. This is intended to
be a static input and cannot be changed on a cycle-by-cycle basis.
When ENDEC = LOW, this is equivalent to ENCDET.
5D
6D
4B
TMODE0
TMODE1
TMODE2
I
TTL
TTL
Transmit Input Data Timing Mode. Determines the timing reference for Tn[7:0],
WSENn and C/Dn on all channels as defined in Table 2 on page 4.
20R
17V
18B
20H
TBERRA
TBERRB
TBERRC
TBERRD
O
Transmit Buffer Error for Channel n. When HIGH indicates that the elastic limit
of the transmit input skew buffer was exceeded, output timing is same as
Rn[7:0]. A LOW indicates correct reception of the 256-byte incrementing
pattern in BIST mode.
1R, 2R
1M, 2M
1J, 2J
PTXA+/-
PTXB+/-
PTXC+/-
PTXD+/-
O
O
PECL
PECL
Primary Differential Serial TX Outputs for Channel n. These pins output
serialized transmit data when PTXENn is HIGH. When PTXENn is LOW, these
output buffers are powered down, the pin is undriven and both pins (+/-) float to
an unknown HIGH state (~ 1.8V). AC-coupling is recommended. External
pull-down resistors are not necessary.
1F, 2F
1T, 2T
1N, 2N
1H, 2H
1E, 2E
RTXA+/-
RTXB+/-
RTXC+/-
RTXD+/-
Redundant Differential Serial TX Outputs for Channel n. These pins output
serialized transmit data when RTXENn is HIGH. When RTXENn is LOW, these
output buffers are powered down, the pin is undriven and both pins (+/-) float to
an unknown HIGH state (~ 1.8V). AC-coupling is recommended. External
pull-down resistors are not necessary.
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
