VSC7216-02
Data Sheet
t
per
REFCLK
WSI
t
t
2
1
Valid
Valid
t
3
WSO
Valid
Valid
t
4
Figure 21. WSI/WSO Timing Waveforms
Table 17. WSI and WSO AC Characteristics
Symbol
Parameter
Min
Typ
Max
Units Condition
t1
Input invalid time after the rising edge of
REFCLK
1.40ns –
0bc
RMODE = 00
ns
1.40ns –
2bc
RMODE = 01
ns
t2
Input valid time after the rising edge of REFCLK –0.10ns –
0bc
RMODE = 00
ns
2.20ns –
2bc
RMODE = 01
ns
t3
t4
REFCLK Rising Edge to TTL output transition
2.20ns
RMODE = 00
ns
5.05ns
(tCQ
)
REFCLK Rising Edge to TTL output transition
(tCQ
2.20ns –
2bc
5.05ns –
2bc
RMODE = 01
ns
)
25 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
