VSC7216-02
Data Sheet
REFCLK
(DUAL = 0)
tPER
REFCLK
(DUAL = 1)
tCQ_MAX
t
t
CQ_MIN
CQ_MIN
Rn[7:0], TBERRn
KCHn, IDLEn, ERRn
PSDETn, RSDETn
Valid
Valid
Valid
Figure 19. Receive Output Timing Waveforms with RMODE = 00 or 01
Table 15. Receive Output AC Characteristics with RMODE = 00 or 01
Symbol
Parameter
Min
Typ
Max
Units Condition
RMODE = 00,
DDT = 2.5V or 3.3V
tCQ
REFCLK Rising Edge to TTL Output Transition
2.20ns –
0bc
5.05ns -
0bc
ns
V
bc = bit clock
tCQ
REFCLK Rising Edge to TTL Output Transition
TTL Output Transition to REFCLK Rising Edge
RMODE = 01,
2.20ns –
2bc
5.05ns -
2bc
ns
ns
V
DDT = 2.5V or 3.3V
bc = bit clock.
tQC
tPER
–
tCQ_MAX
RCLKn
(DUAL = 0)
tPER
RCLKn/RCLKNn
(DUAL = 1)
tCQ_MAX
t
t
CQ_MIN
CQ_MIN
Rn[7:0], TBERRn
KCHn, IDLEn, ERRn
PSDETn, RSDETn
Valid
Valid
Valid
Figure 20. Receive Output Timing Waveforms with RMODE = 10 or 11
Table 16. Receive Output AC Characteristics with RMODE = 10 or 11
Symbol
Parameter
Min
Typ
Max
Units Condition
tCQ
RCLKn/RCLKNn Rising Edge to TTL Output
Transition
–1.25ns +
4bc
1.25ns +
4bc
VDDT = 2.5V,
bc = bit clock.
ns
tQC
DC
TTL Output Transition to RCLKn/RCLKNn
Rising Edge
tPER
tCQ_MAX
–
tPER –
tCQ_MIN
ns
ns
RCLKn/RCLKNn Duty Cycle
50% – 1ns
50% + 1ns
Measured at 1.4V.
24 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
