VSC7216-02
Data Sheet
JTAG
A JTAG access port is provided on the VSC7216-02 Transceiver to facilitate chip-level and board-level test. This port
is compliant with IEEE Standard 1149.1-1990 (subsequently referred to as the “JTAG specification”) with the five
TTL signals listed below:
1. TCK
2. TMS
3. TDI
4. TDO
Test Clock Input
Test Mode Select Input
Test Data Input
Test Data Output
5. TRSTN Test Reset Input
For reliability reasons, a TRSTN input is provided in addition to a power-on reset circuit to initialize the JTAG logic.
This input is named TRST* in the JTAG specification. In accordance with the specification, it is asserted when in the
LOW (logic 0) state. The TRSTN, TDI and TMS input pins have an on-chip high impedance pull-up resistor
connected to the 2.5V V supply so that an undriven input behaves as though a logic 1 were applied.
DD
Pre-emphasis for PECL output, full-swing or half-swing for PECL output, and PECL input termination impedance
selection, can be programmed through the JTAG port. Please contact your local Vitese sales representative for the
latest VSC7216-02 JTAG document for in-cirucit testing, controlling the half versus full swing mode, and the
pre-emphasis mode.
Compatibility with VSC7216-01
The VSC7216-02 is designed to be pin-compatible with the VSC7216-01. The VSC7216-02 uses a 2.5V supply and
has an internal 1.8V regulator that requires an external capacitor on the CREG pin, not found on the VSC7216-01. All
external pin settings on the VSC7216-02 have been configured such that if a VSC7216-02 replaced a VSC7216-01
socket, the defaults would match the VSC7216-01.
The VSC7216-02 offers several new features that may be helpful to the system designer, therefore, latency, skew
timings, and thresholds should be verified and new features considered prior to replacement of the device. Table 11
lists the pin differences between the two devices and assumes the power supply differences of 2.5V and 3.3V.
Table 11: VSC7216-01 Compatibilities
Pin Number
VSC7216-01
Reserved
VSSD
VSC7216-02 Connection Required for VSC7216-01 Compatibility
14Y
6V
CREG
TEST0
Connect a 4.7µF or larger capacitor to ground.
Connect to VSS for normal operation.
Connect to VDD if external receiver termination is used or
8V
VDDD
RREF
populate an external 1% resistor to ground to enable internal receiver termination.
20N
17H
VSST
VDDT
RXFIFO[0]
RXFIFO[1]
Pull LOW to select similar latency setting.
Pull HIGH to select similar latency setting.
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
