VSC7216-02
Data Sheet
Loopback Operation
Loopback control pins, LBENn[1:0], are provided in each channel to internally loopback data paths for on-chip
diagnosis. Both serial and parallel loopback functions are provided.
Table 10. Loopback Mode Selection
LBENn[1:0]
Loopback Mode
Normal Operation
0 0
0 1
1 0
1 1
Internal Parallel Loopback
Internal Serial Loopback
Reserved
When LBENn[1:0] = 10, Serial Loopback mode is selected. The transmitter’s serial transmit data is internally
connected to the receiver’s CRU input. The serial loopback paths are labeled LBTXn in the VSC7216-02 block
diagram on the first page. This allows parallel data on Tn[7:0] to be encoded, serialized, looped back, deserialized
and decoded. This mode is intended for the system to verify functionality of the local VSC7216-02 prior to
attempting to establish an external link. The PTXn and RTXn outputs are unaffected by the state of LBENn[1:0].
When LBENn[1:0] = 01, Parallel Loopback mode is selected. The Rn[7:0] outputs are looped back to the Tn[7:0]
inputs (see Figure 13). WSENn does not have a loopback source and is internally connected to a logic LOW. KCHAR
does not have a loopback source and functions normally. The C/Dn input is obtained by decoding the link status
outputs such that either a data character, special character, or IDLE (K28.5) is transmitted. When the link is in the
LOS or RESYNC state, C/Dn is asserted, and the data path is set to 0xBC so that an IDLE can be sent. For other link
status conditions, C/Dn follows the KCHn status bit, which guarantees that IDLE and special characters are correctly
looped back along with normal data. It also has the effect of looping back the received data as a normal data character
when a disparity error, out-of-band character, or underflow/overflow link status condition occurs.
LBENn[1:0]
8
RXP/Rn
Rn[7:0]
8
3
8B/10B
Decode
Elastic
Buffer
10
IDLEn
KCHn
ERRn
LBTXn
Clk/Data
Recovery
PRXn+
PRXn-
RRXn+
RRXn-
PTXENn
(dec)
PSDETn
RSDETn
1
0
LBTXn
8
≈REFCLK
0
PTXn+
PTXn-
8B/10B
Encode
D
Q
10
8
Tn[7:0]
C/Dn
WSENn
RTXn+
RTXn-
Receiver
RTXENn
≈REFCLK
KCHAR
Transmitter
Figure 13. Parallel Loopback Mode Operation
19 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
