VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing)
TBC
Internal Clock
(from PLL)
T
T
S
S
T(7:0)
C/D
Valid
Valid
Valid
WSEN
Table 10: Transmit Input AC Characteristics with TMODE = 11X
Parameters
Description
Min
Max
Units
Conditions
Measured between the valid data
level of the input and the 1.4V point
of TBC
Input Skew relative to the rising
edge of TBC
TS
—
2.0
bc
Figure 16: Transmit Serial Timing Waveforms
T
T
SDR, SDF
TX0
TX+, TX-
T
LAT
Internal Clock
(from PLL)
Table 11: Transmit Serial AC Characteristics
Parameters
Description
Min
Max
Units
Conditions
Between VOL(MAX) and
VOH(MIN)
TSDR, TSDF
TX+/- rise and fall time
—
330
ps
Latency, REFCLK to TX0
Latency, TBC to TX0
22bc+0.2ns 22bc+0.8ns
36bc+0.0ns 38bc+0.3ns
ENDEC=1 TMODE=000
ENDEC=1 TMODE=10X
TLAT
TJ
bc + ns
ps
Serial data output
Total Jitter (p-p)
IEEE 802.3z Clause 38.69,
Tested on a sample basis
—
—
192
80
Serial data output
Deterministic Jitter (p-p)
IEEE 802.3z Clause 38.69,
Tested on a sample basis
TDJ
ps
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01
Page 21
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