VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Figure 19: RCLK and RCLKN Timing Waveforms with DUAL = 1
T
4
T
3
RCLK
RCLKN
Table 14: General Receive AC Characteristics
Parameters
Description
Min.
Max.
Units
Conditions
Delay between rising edge of
RCLK to rising edge of
RCLKN
10 x TRX
-500
10 x TRX
+500
TRX is the bit period of the
incoming data on Rx.
T3
ps
RCLK to RCLKN skew
10
Deviation of RCLK rising
edge to RCLKN rising edge.
Nominal delay is 10-bit
times.
DT3
T4
-500
500
ps
ps
-----------
Delay=
± ∆T3
fbaud
Whether or not locked to
serial data, independent of
DUAL input.
Period of RCLK and
RCLKN
0.49 x
TREFCLK
0.51 x
TREFCLK
Deviation of
RCLK/RCLKN period from
REFCLK period
Whether or not locked to
serial data, independent of
DUAL input.
DT4
-1.0
1.0
%
TRCLK= TREFCLK ± ∆T4
Between VIL(MAX) and
TR, TF
RLAT
Output rise and fall time
—
2.4
ns
bc+ns
bc
VIH(MIN) into 10pF load
Latency from RX0 to
REFCLK or RCLK
70.5bc-1.6ns
48.5bc-1.6ns 102.5bc+4.1ns
81.5bc+4.1ns
ENDEC=1, recenter only
ENDEC=X, recenter + drift
8B/10B IDLE pattern,
Tested on a sample basis.
(1)
TLOCK
Data acquisition lock time
—
—
—
2500
600
Receive data Total
Jitter Tolerance (p-p)
IEEE 802.3z Clause 38.68,
tested on a sample basis.
TJTD
DJTD
ps
Receive data Deterministic
Jitter Tolerance (p-p)
IEEE 802.3z Clause 38.69,
tested on a sample basis.
370
ps
NOTE: (1) The probability of correct data acquisition and recovery is 95% per FC-PH 4.3 Section 5.3.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52268-0, Rev 3.3
04/10/01
Page 23
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
