ESE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
AC Characteristics
Figure 13: Transmit Input Timing Waveforms with TMODE = 000
REFCLK
(DUAL=0)
REFCLK
(DUAL=1)
Internal Clock
(from PLL)
T
T
T
2
T
2
1
1
T(7:0)
C/D
Valid
Valid
Valid
WSEN
Figure 14: Transmit Input Timing Waveforms with TMODE = 10X
TBC
Internal Clock
(from PLL)
T
T
T
2
T
2
1
1
T(7:0)
C/D
Valid
Valid
Valid
WSEN
Table 9: Transmit Input AC Characteristics with TMODE = 000 or TMODE = 10X
Parameters
Description
Min
Max
Units
Conditions
Input Setup time to the rising
edge of REFCLK or TBC
T1
1.5
—
ns
Measured between the valid data
level of the input and the 1.4V point
of REFCLK or TBC
Input Hold time after the rising
edge of REFCLK or TBC
T2
1.0
—
ns
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Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 20
G52268-0, Rev 3.3
04/10/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
