VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Figure 21: Parametric Measurement Information
Serial Input Rise and Fall Time
TTL Input and Output Rise and Fall Time
VIH(MIN)
80%
20%
VIL(MAX)
Tr
Tf
Tr
Tf
Receiver Input Eye Diagram Jitter Tolerance Mask
Bit Time
Amplitude
Eye Width%
25%
Parametric Test Load Circuit
Serial Output Load
TTL A.C. Output Load
10 pF
Z0 = 50Ω
50Ω
V
– 2.0V
DD
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01
Page 25
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
