ESE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Figure 20: REFCLK Timing Waveforms
TH
VIH(MIN)
VIL(MAX)
REFCLK
TL
Table 15: Reference Clock Requirements
Parameters
Description
Frequency range
Min
Max
Units
Conditions
98
49
136
68
MHz
MHz
DUAL = 0
FR
DUAL = 1
| REFCLK (Tx) - REFCLK (Rx) | =
max offset between Tx and Rx device
REFCLKs on one serial link
FO
Frequency offset
-200
200
ppm
DC
REFCLK duty cycle
35
3
65
—
%
ns
ns
Measured at 1.4V
TH,TL
REFLCK and TBC pulse width
REFCLK rise and fall time
TRCR,TRCF
—
1.5
Between VIL(MAX) and VIH(MIN)
REFCLK Jitter Power
RMS for 10-12 Bit Error Ratio with zero
length external path, tested on a sample
basis
3MHz
REFCLK
Jitter
—
100
ps
PhaseNoise
∫
100Hz
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 24
G52268-0, Rev 3.3
04/10/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
