VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Figure 11: Parallel Loopback Mode Operation
LBEN(1:0)
RXP/R
8
R(7:0)
8
8B/10B
Decode
Elastic
Buffer
10
IDLE
KCH
ERR
LBTX
Clk/Data
Recovery
3
PRX+
PRX-
RRX+
RRX-
PTXEN
LBTX
(dec)
PSDET
RSDET
1
0
8
ªREFCLK
0
PTX+
8B/10B
D Q
10
PTX-
8
T(7:0)
C/D
WSEN
RTX+
RTX-
Encode
RECEIVER
RTXEN
ªREFCLK
1
1
0
KCHAR
PARLOOP
TRANSMITTER
Built-In Self Test Operation
Built-In Self Test operation is enabled when the BIST input is HIGH, which causes TMODE(2:0) to be
internally set to 000. Upon entering BIST mode, the transmitter will issue a Word Sync Sequence in order to
recenter the elasticity buffers in the receive channel. Then the transmitter repeatedly sends a simple 256-byte
incrementing data pattern (prior to 8B/10B encoding) followed by three IDLE characters (K28.5). Note that this
incrementing pattern plus three IDLEs will cause both disparities of each data character and the IDLE character
to be transmitted, and contains a sufficient IDLE density for any application requiring IDLE insertion/deletion.
It is up to the user to enable IDLE insertion/deletion if the receiver’s word clock is not frequency locked to the
transmitter’s REFCLK.
The receiver monitors incoming data for this pattern and indicates if any errors are detected. Correct
reception of the pattern is reported on each receiver’s TBERR output, a LOW means the pattern is being
received correctly and a HIGH means that errors are detected. When BIST transitions from LOW to HIGH,
each TBERR output is initialized HIGH. It will be cleared LOW whenever one or more IDLE characters
followed by all 256 data characters are sequentially received without error, and set HIGH whenever a pattern
mis-match or receiver error is encountered. Received data and associated status will be output as in normal
operation. Please note that Serial Loopback mode and receiver output timing mode selection via RMODE(1:0)
operate independently of BIST mode, but BIST mode disables Parallel Loopback mode.
Figure 12: BIST Mode Operation
LBEN(1:0)
RXP/R
8
R(7:0)
PTXEN
8
3
BIST
Gen
LBTX
8B/10B
Decode
Elastic
Buffer
10
IDLE
KCH
ERR
1
0
8
Clk/Data
Recovery
PTX+ PRX+
PTX- PRX-
RTX+ RRX+
RTX- RRX-
8B/10B
Encode
D Q
10
8
T(7:0)
C/D
WSEN
BIST
Chk
PSDET
RSDET
WORDCLK
RTXEN
ªREFCLK
0
1
0
1
TBERR
TRANSMITTER
RECEIVER
KCHAR
BIST
From Tx
Clock Gen
CGERR
0
}
BIST
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01
Page 17
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
