ESE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Figure 17: Receive Output Timing Waveforms with RMODE = 00 or 01
REFCLK
(DUAL = 0)
T
PER
REFCLK
(DUAL = 1)
T
CQ_max
T
T
QC_min
CQ_min
R(7:0), TBERR
KCH, IDLE, ERR
PSDET, RSDET
Valid
Valid
Valid
Table 12: Receive Output AC Characteristics with RMODE = 00 or 01
Parameters
TCQ
Description
Min
Max
Units
Conditions
REFCLK Rising Edge to TTL
Output Transition
RMODE = 00
bc = Bit Clock
2.58 ns - 0 bc
5.43 ns - 0 bc
5.43 ns - 2 bc
ns
REFCLK Rising Edge to TTL
Output Transition
RMODE = 01
bc = Bit Clock
TCQ
TQC
2.58 ns - 2 bc
ns
ns
TTL Output Transition to
REFCLK Rising Edge
T
PER - TCQ_max
TPER - TCQ_min
Figure 18: Receive Output Timing Waveforms with RMODE = 10 or 11
RCLK
(DUAL = 0)
T
PER
RCLK/RCLKN
(DUAL = 1)
T
CQ_max
T
T
QC_min
CQ_min
R(7:0), TBERR
KCH, IDLE, ERR
PSDET, RSDET
Valid
Valid
Valid
Table 13: Receive Output AC Characteristics with RMODE = 10 or 11
Parameters
Description
Min
Max
1.25 ns + 4 bc
Units
Conditions
RCLK/RCLKN Rising Edge to
TTL Output Transition
RMODE = 10 or 11
bc = Bit Clock
TCQ
-1.25 ns + 4 bc
ns
TTL Output Transition to RCLK/
RCLKN Rising Edge
TPER -
TCQ_max
TQC
DC
T
PER - TCQ_min
50% + 1 ns
ns
ns
RCLK/RCLKN Duty Cycle
50% - 1 ns
Measured at 1.4 V
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Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 22
G52268-0, Rev 3.3
04/10/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
