Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
3.3.6
Input AEQ Control
This register controls the receive AEQ block.
Table 15.
Page 15’h: Input AEQ Control
Bit Name
Access Description
Default
7
6
CAEQENA
R/W
Input AEQ enable
1
1: Use adaptive EQ when EQMAN pin = 0;
use manual EQ when EQMAN pin = 1
0: Use adaptive EQ when EQMAN pin = 1;
use manual EQ when EQMAN pin = 0
CAEQATTENENA
R/W
R/W
Input attenuator control
1: Input attenuator adaptation is on
0: Input attenuator adaptation is off
1
5:3 CAEQSLRATIO
Input AEQ short/long ratio control
111: 7:1
100
110: 6:1
101: 5:1
100: 4:1
011: 3.5:1
010: 3:1
001: 2.5:1
000: 2:1
2:0 CAEQGOAL
R/W
Input AEQ goal control
111: 81:64
100
110: 78:64
101: 75:64
100: 72:64
011: 69:64
010: 66:64
001: 63:64
000: 60:64
3.3.7
Input ISE 1 Long
This register configures the input signal equalization (ISE) stage 1 long time constant.
Table 16.
Page 16’h: Input ISE 1 Long
Bit Name
Access Description
Default
000
7:5 Unused
4:0 CISE1LONG
R
Unused
R/W
ISE 1 long time constant
11111: Maximum
…
00000
00000: Minimum
Revision 2.0
September 2010
Confidential
Page 30
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
