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Subject to Change
VSC7111 Datasheet
Registers
3.3.8
Input ISE 1 Short
This register configures the input signal equalization (ISE) stage 1 short time constant.
Table 17.
Page 17’h: Input ISE 1 Short
Bit Name
Access Description
Default
000
7:5 Unused
4:0 CISE1LONG
R
Unused
R/W
ISE 1 short time constant
11111: Maximum
…
00000
00000: Minimum
3.3.9
Input ISE 2 Long
This register configures the input signal equalization (ISE) stage 2 long time constant.
Table 18.
Page 18’h: Input ISE 2 Long
Bit Name
Access Description
Default
000
7:5 Unused
4:0 CISE2LONG
R
Unused
R/W
ISE 2 long time constant
11111: Maximum
…
00000
00000: Minimum
3.3.10
Input ISE 2 Short
This register configures the input signal equalization (ISE) stage 2 short time constant.
Table 19.
Page 19’h: Input ISE 2 Short
Bit Name
Access Description
Default
000
7:5 Unused
R
Unused
4:0 CISE2SHORT
R/W
ISE 2 short time constant
11111: Maximum
…
00000
00000: Minimum
3.3.11
Output PE 1
This register configures the pre-emphasis amp 1 (PE 1) value and decay time constant
for the selected output.
Table 20.
Page 20’h: Output PE 1
Bit Name
Access Description
Unused
Default
7:6 Unused
R
00
Revision 2.0
September 2010
Confidential
Page 31
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
