Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
3.3.15
PCIe Control
This register configures the PCIe receiver detect state machine.
Table 24.
Page 2E’h: PCIe Control
Bit Name
Access Description
Default
7:4 Unused
R
Unused
0000
0
3
CLOS_DELAY
R/W
PCIe LOS filter delay
0: Long LOS filter delay
1: Short LOS filter delay
2:1 CRXDET_THRES
R/W
R/W
RX Detect Threshold
11: Lowest threshold
…
01
0
00: Highest threshold
0
CPCIE_MODE
Enable PCIe state machine
1: Enabled when not in static mode
0: Disabled when not in static mode
3.3.16
Channel Status
This register provides the RX_DETECT results and LOS status for the selected input.
Table 25.
Page F0’h: Channel Status
Bit Name
Access Description
Default
7:3 Unused
R
R
Unused
00000
2
1
0
CRXDETRES1
1: Output common-mode did pass threshold
after longer delay period
0: Error condition -- output common-mode
never passed threshold
CRXDETRES0
CLOS
R
R
1: Output common-mode did pass threshold
after shorter delay period
0: Output common-mode had not passed
threshold by earlier sampling time
Channel LOS status
1: LOS detected
0: Signal present
3.4
Global Registers
This section provides information about the global device registers. Global settings
apply to all four inputs or outputs and do not use a page address (register address
only).
Revision 2.0
September 2010
Confidential
Page 34
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
