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VSC7111 Datasheet
Registers
3.2
Global Programming
The VSC7111 provides the convenience of Global Programming registers to reduce the
number of instructions required to initialize the device. A global programming register
is associated with each page of registers, with the exception of the one read-only page,
F0'h, that contains the Channel Status and Pin Status registers. A single programming
instruction to one of the global programming registers copies the same value to all the
registers on the associated page. The following table lists the global programming
registers assigned to each page.
Table 8.
Global Programming
Page
Register Name
Global Input ISE1
Global Input ISE2
Global Input Gain
Global Input State
Global Input LOS
Global Output PE1
Global Output PE2
Address Function
Affected Address Range
51'h
52'h
53'h
54'h
55'h
56'h
57'h
Set input ISE1 values
10'h
11'h
12'h
13'h
14'h
20'h
21'h
22'h
00'h–03'h
00'h–03'h
00'h–03'h
00'h–03'h
00'h–03'h
00'h–03'h
00'h–03'h
00'h–03'h
00'h–03'h
Set input ISE2 values
Set input Gain1 and Gain2
Set channel input settings
Set input LOS thresholds
Set output PE1 values
Set output PE2 values
Set output level values
Global Output Level 58'h
Global Output Mode 59'h
Set channel output settings 23'h
Turning on all outputs or inputs simultaneously also generates an instantaneous current
spike. When there is insufficient decoupling capacitance connected to the package pins,
the instantaneous power supply voltage may drop below the minimum level required to
trip the device power-on reset that would change the device configuration.
The following table provides a summary of the global register descriptions.
Table 9.
Register Map, Global Registers
Register
Name
Address
50'h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global MUX Reserved (read only)
MUX selects (0 to 3)
51'h
GlobalInput Reserved (read only)
Gain 1
Input Gain 1
Input Gain 2
52'h
GlobalInput Reserved (read only)
Gain 2
53'h
54'h
Reserved
Reserved (read only)
GlobalInput Reserved Bandwidth Unused
State
Input Buffer
Bandwidth
Terminate Input
(R/W)
Override
to VDD
Power
Off
55'h
56'h
57'h
GlobalInput LOS On
LOS
LOS Threshold
Global
Reserved (read only) PE 1 level
PE 1 decay time constant
PE 2 decay time constant
Output PE 1
Global
Reserved (read only) PE 2 level
Output PE 2
Revision 2.0
September 2010
Confidential
Page 26
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
