Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
Table 9.
Register Map, Global Registers (continued)
Register
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
58'h
Global
Output
Level
Output
Driver
BW
Output
Driver
Current
Output Driver
Bandwidth
Output power level
Override Boost
59'h
Global
Output
Mode
Reserved (read only) Slew
Limit
Jam
Jamval
Drive
Com
Mode
OOB
Enable
Output
Power
Off
5A'h
5B'h
5C'h
5D'h
5E'h
GlobalInput Reserved (read only)
ISE 1 Long
Input ISE 1 Long
Input ISE 1 Short
Input ISE 2 Long
Input ISE 2 Short
GlobalInput Reserved (read only)
ISE 1 Short
GlobalInput Reserved (read only)
ISE 2 Long
GlobalInput Reserved (read only)
ISE 2 Short
Global PCIE Reserved (read only)
Control
LOS
Delay
RX Detect Threshold PCIE_
MODE
5F'h
60'h
Unused
Reserved (read only)
Input AEQ
Control
GAEQ
ENA
GAEQ
ATTEN
ENA
GAEQSLRATIO
GAEQGOAL
61'h–6C'h Reserved (read only)
6D'h
Vitesse use only
6E'h
Reserved (read only)
Vitesse use only
6F'h
70–75'h
76'h
Reserved (read only)
Rx Detect
Delay0
Delay0 value
Delay1 value
Reserved Serial port address
77'h
78'h
Rx Detect
Delay1
Serial
Address
79'h
Reserved (read only)
Vitesse use only
7A'h
7B'h
Vitesse use only
7C–7D'h
7E'h
Reserved (read only)
RevID
Revision ID
Current Page Address
7F'h
Current
Page
3.3
Individual Registers
This section provides information about the individual device registers (address range
00h’-03’h). Each of these registers has a unique page address followed by a register
sub-address (register address) that indicates the input or output number. For example,
Revision 2.0
September 2010
Confidential
Page 27
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
