Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
3.3.4
Input State
This register defines the input enable and termination settings for the selected input.
Table 13.
Page 13’h: Input State
Bit Name
Access Description
Default
7
6
Unused
R/W
R/W
Unused
0
0
CLOWPWR_OVRD
Allow register control of input buffer
bandwidth control
1: CINPLOW_PWR register controls the input
buffer bandwidth/power
0: LOWPWR pin controls the input buffer
bandwidth/power
5:4 Reserved
R/W
R/W
Reserved. Vitesse use only.
00
00
3:2 CINPLOW_PWR
Input bandwidth control
11: Maximum power/bandwidth operation
when CLOWPWR_OVRD = 1
00: Minimum power/bandwidth operation
when CLOWPWR_OVRD = 1
1
0
CINPTERMVDD
CINPPOWEROFF
R/W
R/W
Terminate to VDD
1: Low input common-mode termination
impedance to VDD
0: High input common-mode termination
impedance to VDD (~1 kΩ when input buffer
is enabled, > 50 kΩ when disabled)
0
1
Channel input power off
1: Power off this input
0: Power on this input
3.3.5
Input LOS
This register enables LOS and configures the input LOS threshold value for the selected
input.
Table 14.
Page 14’h: Input LOS
Bit Name
Access Description
Default
7
CLOSON
R/W
Loss of signal (LOS)
1
1: Enabled
0: Disabled
6
Reserved
R/W
R/W
Reserved. Must be set to 1.
1
5:0 CINPLOS
LOS threshold settings
111111: ~300 mV (maximum)
…
100000
011111: ~30 mV (minimum useful value)
011101: 0 mV (minimum)
Revision 2.0
September 2010
Confidential
Page 29
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
