Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
3
Registers
This section provides information about the register maps, register descriptions, and
register tables.
3.1
Individual Register Map
This section provides a register map containing summary descriptions for the individual
registers.
Table 7.
Register Map, Individual Registers
Address
Range
Register
Name
Page
00'h
10'h
11'h
12'h
13'h
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
00'h to 03'h Reserved
Reserved (read only)
00'h to 03'h Input Gain 1 Reserved (read only)
00'h to 03'h Input Gain 2 Reserved (read only)
Input Gain 1
Input Gain 2
00'h to 03'h Unused
Reserved (read only)
00'h to 03'h Input State
Reserved Bandwidth Vitesse use
(R/W)
Input Buffer
Bandwidth
Terminate Input
to VDD
Override
only
Power
Off
14'h
15'h
00'h to 03'h Input LOS
LOS On
LOS Threshold
00'h to 03'h Input AEQ
Control
CAEQ
ENA
CAEQ
ATTEN
ENA
CAEQSLRATIO
CAEQGOAL
16'h
17'h
18'h
19'h
00'h to 03'h Input ISE 1
Long
Reserved (read only)
Reserved (read only)
Reserved (read only)
Reserved (read only)
ISE 1 - Long Time Constant
ISE 1 - Short Time Constant
ISE 2 - Long Time Constant
ISE 2 - Short Time Constant
00'h to 03'h Input ISE 1
Short
00'h to 03'h Input ISE 2
Long
00'h to 03'h Input ISE 2
Short
20'h
21'h
22'h
00'h to 03'h Output PE 1 Reserved (read only) PE 1 level
PE 1 decay time constant
PE 2 decay time constant
00'h to 03'h Output PE 2 RX Detect Threshold
PE 2 level
00'h to 03'h Output
Level
Output
Driver
BW
Output
Driver
Current
Output
Bandwidth
Output power level
Override Boost
23'h
00'h to 03'h Output
Mode
Rx
Detect
Enable
Vitesse
use only
Slew Jam
Limit
Jamval Drive OOB
Output
Power
Off
Com
Enable
Mode
24–2D'h 00'h to 03'h Unused
Reserved (read only)
2E'h 00'h to 03'h PCIE Control Reserved (read only)
LOS
Delay
RX Detect
Threshold
PCIE_
MODE
80–81'h Reserved (read only)
F0'h
00'h to 03'h Channel
Status
Reserved (read only)
RxDet RxDet
LOS
Res1
Res0
Revision 2.0
September 2010
Confidential
Page 25
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
