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Subject to Change
VSC7111 Datasheet
Functional Descriptions
•
A state machine which performs a receive detect at each output and repeats
periodically until it passes, whereupon it activates the corresponding receiver input,
setting the termination to low-impedance state.
To perform a receive detect, the output driver is first placed in the squelched output
mode by the internal logic and then a common-mode pulse is generated and its rise
time measured. A comparator compares the output common-mode voltage to an
internal threshold and flips a latch when the common-mode pulse exceeds the
threshold.
At predefined intervals, which can be adjusted through the Rx Detect Delay0 and Rx
Detect Delay1 registers, the latched comparator output is sampled and, at the end of
the interval count (approximately 50 ms at default setting), the results of the two
samples are available in the Channel Status register bits [2:1]. A value of 11 indicates
a fast rise time (no receiver present), a value of 10 indicates a slow rise time (receiver
present) and 00 and 01 represent error conditions.
After receive detect has passed, the state machine ceases performing periodic receive
detect operations. When an input LOS condition lasting 1 ms or more occurs, the
receive detect state machine will go back to its initial state and start periodically
performing receive detect again. The following illustration shows the PCIe state
machine.
Revision 2.0
September 2010
Confidential
Page 23
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
