Advance Product Information
Subject to Change
VSC7111 Datasheet
Functional Descriptions
For more information about the specific output levels and the values used to select
them, see “Output Level,” page 32.
The VSC7111 provides a function to limit the slew rate of the output drivers. Enabling
the slew limit function increases the rise time and fall time. To enable this function, set
the Output Mode register bit 5.
2.13
Output Signal Suppression and PCIe Electrical Idle
The VSC7111 can be configured to selectively suppress an output signal to reduce
signal noise in a system. When the output signal is suppressed, the true and
complement values are driven to the common-mode value. This signal level is stable
and maintains a DC level that is within ±50 mV.
This function is controlled by bit 0 of the registers on the Output Mode page 23'h. For
more information about the bit values that set the state of the output for normal,
power-off, or suppressed operations, see “Output Mode,” page 33.
VSC7111 has the capability to suppress the output signal in response to an LOS
assertion at the connected input. For more information, see “Input LOS,” page 29. The
purpose of this feature is to propagate out-of-band (OOB) signaling information
through the VSC7111 and is compatible with SAS, SATA, and PCIe operation.
The VSC7111 features an OOB forwarding switch core that duplicates the connections
in the high-speed switch core. This core is used to switch the LOS detect signal. When
bit 1 of the Output Mode register is set to 1, the selected output is suppressed
whenever the connected input asserts an LOS condition. This overrides the current
output state for as long as the LOS from the input remains asserted. After the LOS
condition is removed and the LOS is deasserted, the output assumes whatever state is
present on the currently selected input.
It takes approximately 4 ns for the LOS condition to be propagated from the input to
the output. For more information, see “Output Mode,” page 33.
2.14
PCI-Express Receive Detect
The device can be placed in PCIe mode by setting SCK = 1 and MUXCFG = 0 while in
static mode (IFMODE[1:0] = 11), or by setting the PCIE_MODE register bit to 1 while in
two-wire or four-wire serial interface mode.
To function in a PCIe application, the VSC7111 has three features that are engaged
when the device is placed in PCIe mode:
•
•
The input termination has a setting to produce a low-common-mode impedance at
the input, allowing it to appear as an active receiver from the perspective of a PCIe
transmitter performing a receive detect operation. For more information, see “Input
Power and Termination Impedance,” page 19.
The output driver has the capability to generate a receive-detect pulse and
compare the rise time of that pulse to a criterion that indicates the presence or
absence of an active PCIe receiver at the far end of the line.
Revision 2.0
September 2010
Confidential
Page 22
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
