Advance Product Information
Subject to Change
VSC7111 Datasheet
Product Overview
Figure 1.
Block Diagram
AN[3:2] A[3:2]
2
2
Input EQ
2
2
A[1:0]
Input EQ
Y[3:2]
2
AN[1:0]
Output
Drivers
with PE
Two-wire/
Four-wire
Interface
YN[3:2]
2
Control
Logic
Output Drivers
with PE
2
2
Static Control Pins
YN[1:0] Y[1:0]
The following illustration shows the VSC7111 device in a PCIe Gen 3 buffer application.
The VSC7111 is operating in static (pin-strap) mode with the built-in PCIe receiver
detect state machine. No external control is required. Automatic (adaptive) input
equalization is enabled so that the part is autonomous and self-adjusting.
Figure 2.
Application Diagram
2.5V
> 25” of FR4
at 8.0 Gbps
> 25” of FR4
at 8.0 Gbps
SCK VDD EQMAN
Input A0+
Output Y0+
TX0+
TX0–
RX0+
RX0–
Input A0–
Output Y0–
RX0+
RX0–
Output Y1+
Output Y1–
Input A1+
Input A1–
TX0+
TX0–
PCIe Gen 3
Root
Complex
PCIe Gen 3
End Point
VSC7111
TX1+
TX1–
Input A2+
Input A2–
Output Y2+
Output Y2–
RX1+
RX1–
RX1+
RX1–
Output Y3+
Output Y3–
Input A3+
Input A3–
TX1+
TX1–
MUXCFG VSS
Revision 2.0
September 2010
Confidential
Page 10
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
