VSC6134
Datasheet
3.13.3
Global MPU Register 2 - One-Second Pulse Software Control
Address:
0x002
Register Reset Value:
0x0000
Table 400. Global MPU Register 2 - One-Second Pulse Software Control
Reset
Value
Bit
Name
Access
Description
15
SW_SECONDP
R/W
When configured for software operation (that is,
SECP_SOURCE_SEL, see Table 403, page 367),
this configuration bit is used to generate a
performance monitor one-second pulse under
software control. The one-second pulse is edge
detected in the associated system clock domain and
used internally to transfer the performance monitor
counter values from the system clock domain to the
microprocessor clock domain for access by the
microprocessor. The operation of the one-second
pulse in the hardware and software mode of
operation is summarized in “Performance Monitor
One-Second Pulse,’ page 195.
0
A 0 to 1 transition of this configuration bit generates
a one-second pulse.
14:0
Reserved
RO
0x0000
3.13.4
Global MPU Register 3 - One-Second Pulse MSW Count
Address:
0x003
Register Reset Value:
0x04A2
Table 401. Global MPU Register 3 - One-Second Pulse MSW Count
Reset
Value
Bit
Name
Access
Description
15:0
SECONDP_CNT[31:16]
R/W
The 16 MSW bits of the internal one-second pulse
counter. The value to be programmed depends on
the selected clock domain (see “Performance
Monitor One-Second Pulse,’ page 195).
0x4A2
366 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
