VSC6134
Datasheet
3.13
Global Registers
The global registers and configuration bits are shown in the following sections.
3.13.1
Global MPU Register 0 - Reset and Snapshot
Address:
0x000
Register Reset Value:
0x8C00
Table 398. Global MPU Register 0 - Reset and Snapshot
Reset
Value
Bit
Name
Access
Description
15
SW_RESETN
R/W
Active low software reset. Setting this bit to 0 resets
all the configuration and status registers and
initializes the state machines and the memory blocks
to a known state.
1
Note that global registers are not reset.
14
13
ADD_FIFO_ENC_POINTER_RESET
DROP_FIFO_DEC_POINTER_RESET
R/W
R/W
A 0 to 1 transition of this bit resets the read and write
pointers in the clock crossing and interleaving FIFOs
in the encoder block.
0
0
A 0 to 1 transition of this bit resets the read and write
pointers in the clock crossing and de-interleaving
FIFO’s in the decoder block.
Note that DROP_FIFO_DEC_POINTER_RESET
should not be used in modes where an FEC signal is
received on the Line side. FEC_FORCE_OOF
should be used in this case to reset the FIFO
pointers.
12
11
Reserved
RO
0
1
A_PRESCALER_RESETN
R/W
Active low reset. Setting this bit to 0 resets the
prescaler on the add path.
10
9
D_PRESCALER_RESETN
R/W
R/W
Active low reset. Setting this bit to 0 resets the
prescaler on the drop path.
1
0
DROP_FIFO_ENC_POINTER_RESET
A 0 to 1 transition of this bit resets the read and write
pointers in the clock crossing and interleaving FIFOs
in the encoder block.
8
ADD_FIFO_DEC_POINTER_RESET
R/W
A 0 to 1 transition of this bit resets the read and write
pointers in the clock crossing and de-interleaving
FIFOs in the decoder block.
0
Note that ADD_FIFO_DEC_POINTER_RESET
should not be used in modes where an FEC signal is
received on the client side. FEC_FORCE_OOF
should be used in this case to reset the FIFO
pointers.
7:0
Reserved
RO
0x00
364 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
