VSC6134
Datasheet
Table 404. Global MPU Register 6 - Global Configuration Control 1 (continued)
Reset
Value
Bit
Name
Access
Description
6
FECENC_BYPASS
R/W
0: Normal operation of add encoder
1: Add line FEC encoder is bypassed for SONET/
SDH pass through applications.
0
5:4
DROP_FIFO_MODE[1:0]
R/W
Drop Path FIFO configuration control.
00: SONET/SDH/Tranparent to FEC (OTU) mode is
selected.
00
01: Line FEC or OTU Repeater mode (drop decoder
to add encoder loopback) is selected.
10: Line FEC or OTU Repeater mode (drop decoder
to add encoder loopback) with SONET/SDH mid-
path regeneration is selected.
11: Client FEC to line FEC mode is selected.
3
2
Reserved
RO
0
0
ADD_FEC_PRBS_SEL
R/W
0: Normal data is transmitted on the FEC (DWDM)
interface.
1: Pseudorandom data is transmitted on the FEC
(DWDM) interface.
1
0
ADD_ASYNC
R/W
R/W
0: Add Path Bit Synchronous Mapping mode.
1: Add Path Asynchronous Mapping mode (only
applicable for CBR10G clients).
0
0
DROP_ASYNC
0: Drop Path Bit Synchronous Demapping mode.
1: Drop Path Asynchronous Demapping mode (only
applicable for CBR10G clients).
3.13.8
Global MPU Register 7 - Global Sync Status Mask
Address:
0x007
Register Reset Value:
0xFCC0
Table 405. Global MPU Register 7 - Global Sync Status Mask
Reset
Value
Bit
Name
Access
Description
15
SDH_DROP_FSM
R/W
Mask bit for the drop path SDH/SONET frame sync.
0: Allow frame sync to generate interrupt
1: Mask interrupt
1
1
1
1
14
13
12
SDH_ADD_FSM
FEC_RX_FSM
OTU_TX_FSM
R/W
R/W
R/W
Mask bit for the add path SDH/SONET frame sync.
0: Allow frame sync to generate interrupt
1: Mask interrupt
Mask bit for the drop path FEC frame sync.
0: Allow frame sync to generate interrupt
1: Mask interrupt
Mask bit for the add path ODU frame sync.
0: Allow frame sync to generate interrupt
1: Mask interrupt
369 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
