VSC6134
Datasheet
Table 405. Global MPU Register 7 - Global Sync Status Mask (continued)
Reset
Value
Bit
Name
Access
Description
11
OTU_RX_MFSM
R/W
Mask bit for the add path OTU frame sync after the
clock crossing FIFO.
1
0: Allow frame sync to generate interrupt
1: Mask interrupt
10
OTU_RX_FSTARTM
R/W
Mask bit for the add path OTU codeword frame start
after the clock crossing FIFO.
1
0: Allow frame sync to generate interrupt
1: Mask interrupt
9:8
7
Reserved
RO
00
1
SECONDPSM
R/W
Mask bit for the one-second pulse sync.
0: Allow one-second pulse to generate interrupt
1: Mask interrupt
6
RESET_RDYM
Reserved
R/W
RO
Mask bit for the RESET_RDY signal following a
hardware or software reset of the device.
0: Allow RESET_RDY to generate interrupt
1: Mask interrupt
1
5:0
0x00
3.13.9
Global MPU Register 8 - Global Sync Status
Address:
0x008
Register Reset Value:
0x0000
Table 406. Global MPU Register 8 - Global Sync Status
Reset
Value
Bit
Name
Access
Description
15
SDH_DROP_FSS
R/W
Interrupt status bit for the drop path SDH/SONET
frame sync.
0
1: Indicates that a frame sync is detected.
14
SDH_ADD_FSS
R/W
Interrupt status bit for the add path SDH/SONET
frame sync.
0
1: Indicates that a frame sync is detected.
13
12
11
FEC_RX_FSS
OTU_TX_FSS
OTU_RX_MFSS
R/W
R/W
R/W
Interrupt status bit for the drop path FEC frame sync.
1: Indicates that a frame sync is detected.
0
0
0
Interrupt status bit for the add path OTU frame sync.
1: Indicates that a frame sync is detected.
Interrupt status bit for the add path OTU frame sync
after the clock crossing FIFO.
1: Indicates that a frame sync is detected.
10
OTU_RX_FSTARTS
Reserved
R/W
RO
Interrupt status bit for the add path codeword frame
start after the clock crossing FIFO.
1: Indicates that a frame sync is detected.
0
9:8
00
370 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
