VSC6134
Datasheet
3.12.7
Drop PRBS Checker Configuration Register
Address:
0x300
Register Reset Value:
0x0000
Table 394. Drop PRBS Checker Configuration Register
Reset
Value
Bit
Name
Access
Description
15
PRBSCHK_ENA
R/W
Enable PRBS checker on the line side interface.
0
1: Enable
0: Disable
14:13
PRBSCHK_SEL[1:0]
R/W
Select sequence length.
00: 215 – 1
00
01: 220 – 1
10: 223 – 1
11: 231 – 1
12
PRBSCHK_INV
Reserved
R/W
RO
Compare input data with inverted sequence
1: No invert
0: Invert
0
11:0
0x000
3.12.8
Drop PRBS Checker Interrupt Mask Register
Address:
0x301
Register Reset Value:
0x0000
Table 395. Drop PRBS Checker Interrupt Mask Register
Reset
Value
Bit
Name
Access
Description
15
PRBSCHK_SYNCM
R/W
Mask bit for the PRBSCHK_SYNCS status bit.
1: Mask interrupt
1
0: Allow status bit to generate interrupts
14
PRBSCHK_ERRM
Reserved
R/W
RO
Mask bit fo the PRBSCHK_ERRS status bit.
1: Mask interrupt
0: Allow status bit to generate interrupts
1
13:0
0x000
362 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
